1. Technical Field
The invention relates to printed circuitry, and more particularly to a printed circuit board compensating for capacitance characteristics of a via stub.
2. Description of Related Art
A printed circuit board (PCB), such as a multilayer PCB used with a high-level server main board, a motherboard, or a backplane has signal layers, ground layers and source layers. Effective via technology is thus important in the PCB design.
As shown in FIGS. 5A and 5B, a lateral view and cross section of a PCB 1 such as multilayer PCB, PCB 1 has a plurality of copper foil layers 11, a first line layer 12, a second line layer 13, a pair of symmetrical vias 14A, 14B, an isolation layer 15 and a plurality of line layers 16. Each copper foil layer 11 has a symmetrical pair of void holes 11A, 11B both of which are disposed between the first line layer 12, the second line layer 13 and each line layer 16. The isolation layer 15 is disposed between each copper foil layer 11, the first line layer 12, the second line layer 13 and each line layer 16. The first line layer 12 is disposed on the second line layer 13. The vias 14A, 14B are disposed through the first line layer 12, the second line layer 13, the avoiding holes 11A, 11B and the isolation layer 15.
The first line layer 12 and the second line layer 13 have a pair of symmetrical first conductors 12A, 12B, symmetrical second conductors 13A, 13B, symmetrical first signal lines L1A, L1B, symmetrical second signal lines L2A, L2B. The first conductors 12A, 12B and the second conductors 13A, 13B, such as solder pads, are disposed around the vias 14A, 14B, respectively and correspond to the through holes 11A, 11B. The first signal lines L1A, L1B and the second signal lines L2A, L2B are coupled to the first conductors 12A, 12B and the second conductors 13A, 13B, respectively.
When the first signal lines L1A, L1B receive a pair of input signals S1, the input signals are transmitted through the first conductors 12A, 12B, the vias 14A, 14B, the second conductors 13A, 13B and output from the second signal lines L2A, L2B. The vias 14A, 14B below the second signal line layer 13 do not path the input signal S1, thus creating a via stub structure W, as shown in FIG. 5B, elevating capacitance and lowering impedance. thereby preventing the high frequency of the input signal S1 from passing, slowing the time wave. As shown in FIG. 5C, a channel response oscillogram, a curve C1 decays before the frequency reaches 9 GHz. Vias such as 14A, 14B, below the second signal line layer 13 and the second signal lines L2A, L2B act as branches, and the part of the input signal S1 is input to the vias 14A, 14B, and reflected back therethrough to generate multiple reflection, adding the original input signal S1 by the second signal lines L2A, L2B to bad effect, as shown in FIG. 5D and FIG. 5E. FIG. 5D is a serial signal eye diagram of the signal path including via stub structure W, causing input signal S1 to experience severe jitter and resulting high noise. FIG. 5E shows a serial signal eye diagram of the signal path with no via stub structure W.
FIG. 6 shows, in an attempt to improve the described problem, implementation of a process, after copper-plating of the vias, in which a drill D creates holes from line layers 16 of the PCB 1 to the first line layer 12 to completely clear the via stub structure W and reduce its effect.
However, the added process complicates manufacture of the PCB 1, and difficulty in ensuring precision of drill D positioning of the vias can result in decreased yield and increased costs.
What is needed, therefore, is a printed circuit board compensating for capacitance characteristics of a via stub requiring no added process.